68 lines
3 KiB
Markdown
68 lines
3 KiB
Markdown
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## Circuit2Verilog Module
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**Primary Contributors:**
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1. James H - J Yeh, Ph.D.
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2. Satvik Ramaprasad
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## Introduction
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This is an experimental module which generates verilog netlist (structural
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verilog) given the circuit. Currently, the module generates fully functional
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verilog code for basic circuits. For complex circuit, additional (manual) work
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may need to be done in order to make it work. We are continuously improving this
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module to work with more and more complex circuits.
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# Algorithm
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The basic algorithm is fairly straight forward. We have the circuit graph in
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memory. We just need to convert this graph into verilog netlist. It is done by
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performing a DFS on the circuit graph. The DFS involves the following steps
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1. Creating verilog wires as and when required
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2. Connecting verilog wires in element instantiations
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## Some background information
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The different sub circuits form a DAG (Directed Acyclic Graph) or dependency
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graph. Each sub circuit itself (called scope internally) is actually a (cyclic)
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graph on its own. Therefore the verilog generation is done in a 2 step DFS
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approach. The first DFS is performed on the dependency graph. The second DFS is
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done on individual sub circuit (scope).
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## Code/Algorithm workflow
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1. `exportVerilog()` - entry point
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2. `exportVerilogScope()` - DFS(1) on Sub Circuits Dependency Graph
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1. Set Verilog Labels for all elements
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2. `generateHeader()` - Generates Module Header
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3. `generateOutputList()` - Output Output List
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4. `generateInputList()` - Generates Input List
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5. `processGraph()` - DFS(2) on individual subcircuit/scope
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1. DFS starts from inputs
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2. Calls `processVerilog()` on all circuit elements (graph nodes) - resolves label names and adds neighbors to DFS stack.
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3. Calls `generateVerilog()` on all circuit elements to get final verilog.
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6. Generate Wire initializations
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## Functions
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**Verilog Module Functions:**
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1. `verilog.exportVerilog()` - Entry point
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1. `verilog.exportVerilogScope()` - Recursive DFS function on subcircuit graph
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1. `verilog.processGraph()` - Iterative DFS function on subcircuit scope
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1. `verilog.resetLabels()` - Resets labels in scope
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1. `verilog.setLabels()` - Sets labels in scope
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1. `verilog.generateHeader()` - Generates Verilog Module Header
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1. `verilog.generateInputList()` - Generates Verilog Module Input List
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1. `verilog.generateOutputList()` - Generates Verilog Module Output List
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1. `verilog.sanitizeLabel()` - Sanitizes label for node/wire
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1. `verilog.generateNodeName()` - Helper function to resolve node/wire name
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**CircuitElement Functions:**
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These functions can be overriden by derived classes.
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1. `CircuitElement.prototype.processVerilog()` - Graph algorithm to resolve verilog wire labels
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1. `CircuitElement.prototype.verilogName()` - Generate verilog name
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1. `CircuitElement.prototype.generateVerilog()` - Generate final verilog code
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1. `CircuitElement.prototype.verilogType` - Verilog type name
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1. `CircuitElement.moduleVerilog` - Custom module verilog for elements
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