507 lines
18 KiB
JavaScript
507 lines
18 KiB
JavaScript
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/*
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# Primary Developers
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1) James H-J Yeh, Ph.D.
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2) Satvik Ramaprasad
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refer verilog_documentation.md
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*/
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function generateVerilog() {
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var data = verilog.exportVerilog();
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console.log(data);
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download(projectName + ".v", data);
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}
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verilog = {
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// Entry point to verilog generation
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// scope = undefined means export all circuits
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exportVerilog:function(scope = undefined){
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var dependencyList = {};
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// Reset Verilog Element State
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for (var i = 0; i < circuitElementList.length; i++) {
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if (window[circuitElementList[i]].resetVerilog) {
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window[circuitElementList[i]].resetVerilog();
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}
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}
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// List of devices under test for which testbench needs to be created
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var DUTs = [];
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var SubCircuitIds = new Set();
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// Generate SubCircuit Dependency Graph
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for (id in scopeList) {
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dependencyList[id] = scopeList[id].getDependencies();
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for (var i = 0; i < scopeList[id].SubCircuit.length; i++) {
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SubCircuitIds.add(scopeList[id].SubCircuit[i].id);
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}
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}
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for(id in scopeList) {
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if(!SubCircuitIds.has(id))
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DUTs.push(scopeList[id]);
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}
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// DFS on SubCircuit Dependency Graph
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var visited = {};
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var elementTypesUsed = {};
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var output = "";
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if(scope) {
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// generate verilog only for scope
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output += this.exportVerilogScope(scope.id,visited,dependencyList, elementTypesUsed);
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}
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else {
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// generate verilog for everything
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for (id in scopeList) {
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output += this.exportVerilogScope(id,visited,dependencyList, elementTypesUsed);
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}
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}
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// Add Circuit Element - Module Specific Verilog Code
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for(var element in elementTypesUsed) {
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// If element has custom verilog
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if (window[element].moduleVerilog) {
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output += window[element].moduleVerilog();
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}
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}
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var report = this.generateReport(elementTypesUsed) + "\n";
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var testbench = this.generateTestBenchCode(DUTs);
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return report + testbench + output;
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},
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generateReport: function(elementTypesUsed) {
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var output = "";
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output += "/**\n"
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output += " * This is an autogenerated netlist code from CircuitVerse. Verilog Code can be\n"
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output += " * tested on https://www.edaplayground.com/ using Icarus Verilog 0.9.7. This is an\n"
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output += " * experimental module and some manual changes make need to be done in order for\n"
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output += " * this to work.\n"
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output += " *\n"
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output += " * If you have any ideas/suggestions or bug fixes, raise an issue\n"
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output += " * on https://github.com/CircuitVerse/CircuitVerse/issues/new/choose\n"
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output += " */\n"
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output += "\n";
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output += '/*\n';
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output += sp(1) + "Element Usage Report\n";
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for(var elem in elementTypesUsed) {
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if(elem == "Node")continue;
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output += `${sp(2)}${elem} - ${elementTypesUsed[elem]} times\n`;
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}
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output += '*/\n';
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output += "\n";
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var instructions = "";
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output += '/*\n';
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output += sp(1) + "Usage Instructions and Tips\n";
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instructions += sp(2) + "Labels - Ensure unique label names and avoid using verilog keywords\n";
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instructions += sp(2) + "Warnings - Connect all optional inputs to remove warnings\n";
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for(var elem in elementTypesUsed) {
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// If element has custom instructions
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if (window[elem].verilogInstructions) {
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instructions += indent(2, window[elem].verilogInstructions());
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}
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}
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output += instructions
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output += '*/\n';
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return output;
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},
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generateTestBenchCode: function(DUTs) {
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if(DUTs.length == 0)return "";
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var output = "// Sample Testbench Code - Uncomment to use\n";
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output += "\n/*\n";
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output += "module TestBench();\n";
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var registers = {};
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var wires = {};
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for(var i = 1; i <= 32; i++)
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registers[i] = new Set();
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for(var i = 1; i <= 32; i++)
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wires[i] = new Set();
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var clocks = new Set();
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var inputs = new Set();
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var outputs = new Set();
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var deviceInstantiations = "";
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for(var i = 0; i < DUTs.length; i++) {
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var DUT = DUTs[i];
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for(var j = 0;j < DUT.Input.length; j++){
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var inp = DUT.Input[j];
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registers[inp.bitWidth].add(inp.label);
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inputs.add(inp.label);
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}
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for(var j = 0;j < DUT.Output.length; j++){
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var out = DUT.Output[j];
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wires[out.bitWidth].add(out.label);
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outputs.add(out.label);
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}
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for(var j=0;j<DUT.Clock.length;j++){
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var inp = DUT.Clock[j];
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registers[1].add(inp.label);
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clocks.add(inp.label);
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}
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var circuitName = this.sanitizeLabel(DUT.name);
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var dutHeader = this.generateHeaderHelper(DUT);
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deviceInstantiations += `${sp(1)}${circuitName} DUT${i}${dutHeader}\n`;
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}
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output += "\n"
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// Generate Reg Initialization Code
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for (var bitWidth = 1; bitWidth<= 32; bitWidth++){
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if(registers[bitWidth].size == 0)
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continue;
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var regArray = [...registers[bitWidth]];
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if(bitWidth == 1)
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output += `${sp(1)}reg ${regArray.join(", ")};\n`;
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else
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output += `${sp(1)}reg [${bitWidth-1}:0] ${regArray.join(", ")};\n`;
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}
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output += "\n"
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// Generate Wire Initialization Code
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for (var bitWidth = 1; bitWidth<= 32; bitWidth++){
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if(wires[bitWidth].size == 0)
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continue;
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var wireArray = [...wires[bitWidth]];
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if(bitWidth == 1)
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output += `${sp(1)}wire ${wireArray.join(", ")};\n`;
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else
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output += `${sp(1)}wire [${bitWidth-1}:0] ${wireArray.join(", ")};\n`;
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}
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output += "\n"
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output += deviceInstantiations;
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if(clocks.size) {
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output += `${sp(1)}always begin\n`;
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output += `${sp(2)}#10\n`;
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for(var clk of clocks)
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output += `${sp(2)}${clk} = 0;\n`;
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output += `${sp(2)}#10\n`;
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for(var clk of clocks)
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output += `${sp(2)}${clk} = 1;\n`;
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output += `${sp(1)}end\n`;
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output += '\n';
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}
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output += `${sp(1)}initial begin\n`;
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// Reset inputs to 0
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for(var inp of inputs){
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output += `${sp(2)}${inp} = 0;\n`;
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}
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output += '\n';
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output += `${sp(2)}#15\n`;
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for(var out of outputs) {
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output += `${sp(2)}$display("${out} = %b", ${out});\n`;
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}
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output += '\n';
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output += `${sp(2)}#10\n`;
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for(var out of outputs) {
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output += `${sp(2)}$display("${out} = %b", ${out});\n`;
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}
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output += '\n';
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output += `${sp(2)}$finish;\n\n`;
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output += `${sp(1)}end\n`;
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output += "endmodule\n";
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output += "\n*/\n";
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return output;
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},
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// Recursive DFS function
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exportVerilogScope: function(id,visited,dependencyList, elementTypesUsed){
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// Already Visited
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if (visited[id]) return "";
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// Mark as Visited
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visited[id] = true;
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var output = "";
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// DFS on dependencies
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for (var i = 0; i < dependencyList[id].length; i++)
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output += this.exportVerilogScope(dependencyList[id][i],visited,dependencyList, elementTypesUsed)+"\n";
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var scope = scopeList[id];
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// Initialize labels for all elements
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this.resetLabels(scope);
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this.setLabels(scope);
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output += this.generateHeader(scope);
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output += this.generateOutputList(scope); // generate output first to be consistent
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output += this.generateInputList(scope);
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// Note: processGraph function populates scope.verilogWireList
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var res = this.processGraph(scope, elementTypesUsed);
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// Generate Wire Initialization Code
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for (var bitWidth = 1; bitWidth<= 32; bitWidth++){
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var wireList = scope.verilogWireList[bitWidth];
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// Hack for splitter
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wireList = wireList.filter(x => !x.includes("["))
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if(wireList.length == 0)
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continue;
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if(bitWidth == 1)
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output += " wire " + wireList.join(", ") + ";\n";
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else
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output += " wire [" +(bitWidth-1)+":0] " + wireList.join(", ") + ";\n";
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}
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// Append Wire connections and module instantiations
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output += res;
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// Append footer
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output += "endmodule\n";
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return output;
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},
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// Performs DFS on the graph and generates netlist of wires and connections
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processGraph: function(scope, elementTypesUsed){
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// Initializations
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var res = "";
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scope.stack = [];
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scope.verilogWireList = [];
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for(var i = 0; i <= 32; i++)
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scope.verilogWireList.push(new Array());
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var verilogResolvedSet = new Set();
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// Start DFS from inputs
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for (var i = 0; i < inputList.length; i++) {
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for (var j = 0; j < scope[inputList[i]].length; j++) {
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scope.stack.push(scope[inputList[i]][j]);
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}
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}
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// Iterative DFS on circuit graph
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while (scope.stack.length) {
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if (errorDetected) return;
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var elem = scope.stack.pop();
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if(verilogResolvedSet.has(elem))
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continue;
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// Process verilog creates variable names and adds elements to DFS stack
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elem.processVerilog();
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// Record usage of element type
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if(elem.objectType != "Node") {
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if(elementTypesUsed[elem.objectType])elementTypesUsed[elem.objectType]++;
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else elementTypesUsed[elem.objectType] = 1;
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}
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if(elem.objectType!="Node" && elem.objectType!="Input" && elem.objectType!="Clock") {
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verilogResolvedSet.add(elem);
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}
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}
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// Generate connection verilog code and module instantiations
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for(var elem of verilogResolvedSet) {
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res += " " + elem.generateVerilog() + "\n";
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}
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return res;
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},
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resetLabels: function(scope){
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for(var i=0;i<scope.allNodes.length;i++){
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scope.allNodes[i].verilogLabel="";
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}
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},
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// Sets labels for all Circuit Elements elements
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setLabels: function(scope=globalScope){
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/**
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* Sets a name for each element. If element is already labeled,
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* the element is used directly, otherwise an automated label is provided
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* sanitizeLabel is a helper function to escape white spaces
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*/
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for(var i=0;i<scope.Input.length;i++){
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if(scope.Input[i].label=="")
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scope.Input[i].label="inp_"+i;
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else
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scope.Input[i].label=this.sanitizeLabel(scope.Input[i].label)
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// copy label to node
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scope.Input[i].output1.verilogLabel = scope.Input[i].label;
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}
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for(var i=0;i<scope.ConstantVal.length;i++){
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if(scope.ConstantVal[i].label=="")
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scope.ConstantVal[i].label="const_"+i;
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else
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scope.ConstantVal[i].label=this.sanitizeLabel(scope.ConstantVal[i].label)
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// copy label to node
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scope.ConstantVal[i].output1.verilogLabel=scope.ConstantVal[i].label;
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}
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// copy label to clock
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for(var i = 0; i < scope.Clock.length; i++) {
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if (scope.Clock[i].label == "")
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scope.Clock[i].label = "clk_"+i;
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else
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scope.Clock[i].label=this.sanitizeLabel(scope.Clock[i].label);
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scope.Clock[i].output1.verilogLabel = scope.Clock[i].label;
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}
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for(var i=0;i<scope.Output.length;i++){
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if(scope.Output[i].label=="")
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scope.Output[i].label="out_"+i;
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else
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scope.Output[i].label=this.sanitizeLabel(scope.Output[i].label)
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}
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for(var i=0;i<scope.SubCircuit.length;i++){
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if(scope.SubCircuit[i].label=="")
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scope.SubCircuit[i].label=scope.SubCircuit[i].data.name+"_"+i;
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else
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scope.SubCircuit[i].label=this.sanitizeLabel(scope.SubCircuit[i].label)
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}
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for(var i=0;i<moduleList.length;i++){
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var m = moduleList[i];
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for(var j=0;j<scope[m].length;j++){
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scope[m][j].verilogLabel = this.sanitizeLabel(scope[m][j].label) || (scope[m][j].verilogName()+"_"+j);
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}
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}
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},
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generateHeader:function(scope=globalScope){
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// Example: module HalfAdder (a,b,s,c);
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||
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|
var res="\nmodule " + this.sanitizeLabel(scope.name);
|
||
|
|
res += this.generateHeaderHelper(scope);
|
||
|
|
return res;
|
||
|
|
},
|
||
|
|
generateHeaderHelper:function(scope=globalScope) {
|
||
|
|
// Example: (a,b,s,c);
|
||
|
|
var res="(";
|
||
|
|
var pins = [];
|
||
|
|
for(var i=0;i<scope.Output.length;i++){
|
||
|
|
pins.push(scope.Output[i].label);
|
||
|
|
}
|
||
|
|
for(var i=0;i<scope.Clock.length;i++){
|
||
|
|
pins.push(scope.Clock[i].label);
|
||
|
|
}
|
||
|
|
for(var i=0;i<scope.Input.length;i++){
|
||
|
|
pins.push(scope.Input[i].label);
|
||
|
|
}
|
||
|
|
res += pins.join(", ");
|
||
|
|
res += ");\n";
|
||
|
|
return res;
|
||
|
|
},
|
||
|
|
generateInputList:function(scope=globalScope){
|
||
|
|
var inputs={}
|
||
|
|
for(var i = 1; i <= 32; i++)
|
||
|
|
inputs[i] = [];
|
||
|
|
|
||
|
|
for(var i=0;i<scope.Input.length;i++){
|
||
|
|
inputs[scope.Input[i].bitWidth].push(scope.Input[i].label);
|
||
|
|
}
|
||
|
|
|
||
|
|
for(var i=0;i<scope.Clock.length;i++){
|
||
|
|
inputs[scope.Clock[i].bitWidth].push(scope.Clock[i].label);
|
||
|
|
}
|
||
|
|
|
||
|
|
var res="";
|
||
|
|
for (bitWidth in inputs){
|
||
|
|
if(inputs[bitWidth].length == 0) continue;
|
||
|
|
if(bitWidth==1)
|
||
|
|
res+=" input "+ inputs[1].join(", ") + ";\n";
|
||
|
|
else
|
||
|
|
res+=" input ["+(bitWidth-1)+":0] "+ inputs[bitWidth].join(", ") + ";\n";
|
||
|
|
}
|
||
|
|
|
||
|
|
return res;
|
||
|
|
},
|
||
|
|
generateOutputList:function(scope=globalScope){
|
||
|
|
// Example 1: output s,cout;
|
||
|
|
var outputs={}
|
||
|
|
for(var i=0;i<scope.Output.length;i++){
|
||
|
|
if(outputs[scope.Output[i].bitWidth])
|
||
|
|
outputs[scope.Output[i].bitWidth].push(scope.Output[i].label);
|
||
|
|
else
|
||
|
|
outputs[scope.Output[i].bitWidth] = [scope.Output[i].label];
|
||
|
|
}
|
||
|
|
var res="";
|
||
|
|
for (bitWidth in outputs){
|
||
|
|
if(bitWidth==1)
|
||
|
|
res+=" output "+ outputs[1].join(", ") + ";\n";
|
||
|
|
else
|
||
|
|
res+=" output ["+(bitWidth-1)+":0] "+ outputs[bitWidth].join(", ") + ";\n";
|
||
|
|
}
|
||
|
|
|
||
|
|
return res;
|
||
|
|
},
|
||
|
|
sanitizeLabel: function(name){
|
||
|
|
// return name.replace(/ Inverse/g, "_inv").replace(/ /g , "_");
|
||
|
|
var temp = name;
|
||
|
|
//if there is a space anywhere but the last place
|
||
|
|
//replace spaces by "_"
|
||
|
|
//last space is required for escaped id
|
||
|
|
if (temp.search(/ /g) < temp.length-1 && temp.search(/ /g) >= 0) {
|
||
|
|
temp = temp.replace(/ Inverse/g, "_inv");
|
||
|
|
temp = temp.replace(/ /g , "_");
|
||
|
|
}
|
||
|
|
//if first character is not \ already
|
||
|
|
if (temp.substring(0,1).search(/\\/g) < 0) {
|
||
|
|
//if there are non-alphanum_ character, or first character is num, add \
|
||
|
|
if (temp.search(/[\W]/g) > -1 || temp.substring(0,1).search(/[0-9]/g) > -1)
|
||
|
|
temp = "\\" + temp + " ";
|
||
|
|
}
|
||
|
|
return temp;
|
||
|
|
},
|
||
|
|
/*
|
||
|
|
sanitizeLabel: function(name){
|
||
|
|
// Replace spaces by "_"
|
||
|
|
name = name.replace(/ /g , "_");
|
||
|
|
// Replace Hyphens by "_"
|
||
|
|
name = name.replace(/-/g , "_");
|
||
|
|
// Replace Colons by "_"
|
||
|
|
name = name.replace(/:/g , "_");
|
||
|
|
// replace ~ with inv_
|
||
|
|
name = name.replace(/~/g , "inv_");
|
||
|
|
// Shorten Inverse to inv
|
||
|
|
name = name.replace(/Inverse/g , "inv");
|
||
|
|
|
||
|
|
// If first character is a number
|
||
|
|
if(name.substring(0, 1).search(/[0-9]/g) > -1) {
|
||
|
|
name = "w_" + name;
|
||
|
|
}
|
||
|
|
|
||
|
|
// if first character is not \ already
|
||
|
|
if (name[0] != '\\') {
|
||
|
|
//if there are non-alphanum_ character, add \
|
||
|
|
if (name.search(/[\W]/g) > -1)
|
||
|
|
name = "\\" + name;
|
||
|
|
}
|
||
|
|
return name;
|
||
|
|
},
|
||
|
|
*/
|
||
|
|
generateNodeName: function(node, currentCount, totalCount) {
|
||
|
|
if(node.verilogLabel) return node.verilogLabel;
|
||
|
|
var parentVerilogLabel = node.parent.verilogLabel;
|
||
|
|
var nodeName;
|
||
|
|
if(node.label) {
|
||
|
|
nodeName = verilog.sanitizeLabel(node.label);
|
||
|
|
}
|
||
|
|
else {
|
||
|
|
nodeName = (totalCount > 1) ? "out_" + currentCount: "out";
|
||
|
|
}
|
||
|
|
if (parentVerilogLabel.substring(0,1).search(/\\/g) < 0)
|
||
|
|
return (parentVerilogLabel) + "_" + nodeName;
|
||
|
|
else
|
||
|
|
return (parentVerilogLabel.substring(0,parentVerilogLabel.length-1)) + "_" + nodeName + " ";
|
||
|
|
|
||
|
|
}
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
Helper function to generate spaces for indentation
|
||
|
|
*/
|
||
|
|
function sp(indentation) {
|
||
|
|
return " ".repeat(indentation * 2);
|
||
|
|
}
|
||
|
|
|
||
|
|
/*
|
||
|
|
Helper function to indent paragraph
|
||
|
|
*/
|
||
|
|
function indent(indentation, string) {
|
||
|
|
var result = string.split('\n');
|
||
|
|
if(result[result.length - 1] == '') {
|
||
|
|
result.pop();
|
||
|
|
result = result.map(x => sp(indentation) + x).join("\n");
|
||
|
|
result += '\n';
|
||
|
|
return result;
|
||
|
|
}
|
||
|
|
return result.map(x => sp(indentation) + x).join("\n");
|
||
|
|
}
|